1. Technical Field
This disclosure generally relates to semiconductor devices, and more specifically to asymmetric multi-gated transistors and methods for forming.
2. Background
The use of multi-gated transistors is one option that semiconductor manufacturers have proposed to facilitate continuing scaling of complementary metal-oxide semiconductor (CMOS) technology. A multi-gated transistor which has gates placed on multiple sides of the transistor, allows smaller device dimensions and higher electrical current that can be switched at higher speeds. One type of multi-gated transistor is a fin field effect transistor (FinFET) that has multiple gates surrounding a semiconductor fin. A typical multi-gated FinFET has a symmetric structure and fixed device characteristics. However, for some applications, it is desirable to have an asymmetric multi-gated FinFET. Depending on the power supply, the characteristics of the asymmetric FinFET can be adjusted to achieve an optimal tradeoff between power consumption and device performance. For example, when the FinFET is powered by a battery, low power consumption requirements usually overweigh performance requirements. On the other hand, when the FinFET is powered by an external AC supply, high performance is usually desired.
A drawback with currently available asymmetric multi-gated FinFETs is that the methods to form these transistors are complicated and costly. For instance, these methods usually require an extra masking level and/or are complicated processes.